1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. Particularly, the present invention relates to a recess channel transistor having a gate electrode formed in a groove and a manufacturing method thereof.
2. Description of the Related Art
A gate length of a cell transistor in a dynamic random access memory (DRAM) has been shortened with a miniaturization of a DRAM cell. When the gate length of the cell transistor is shortened, a threshold voltage Vt is decreased due to a short-channel effect. In order to keep transistor characteristics, a method is known of increasing an impurity concentration of a substrate. However, in this case, change in impurity concentration is abrupt in a junction portion, so that the intensity of an electric field applied to the junction portion is increased. This causes the increase of leakage current. The increase of the leakage current is led to the reduction of a refresh cycle tREF, which means deterioration of a data holding characteristic.
In order to avoid the above-mentioned problems, a transistor (called a groove gate transistor and a recess channel transistor) is proposed in which the gate electrode is formed to fill a groove (recess) formed in a semiconductor substrate, as described in “The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond” by J. Y. KIM et al, (Symp. on VLSI Tech., pp. 11-12, 2003). In this case, a channel is formed along a bottom substrate of the recess. Therefore, a substantial channel length can be elongated and suppression of the short-channel effect can be realized.
Also, a semiconductor device of a conventional example is disclosed in Japanese Laid Open Patent Application (JP-P2003-78033A). In the semiconductor device of this conventional example, a gate electrode is formed in the groove in the semiconductor substrate via a gate insulating film. Side walls of an insulating film are formed in an upper portion of the groove to be thicker than the gate insulating film. The gate electrode is formed in a bottom portion of the groove, i.e., downwardly from bottom ends of the side walls. An upper surface of the gate electrode is positioned lower than a substrate surface.
A method of manufacturing a general recess channel transistor will be described with reference to FIGS. 1A to 1E. As shown in FIG. 1A, an element isolation structure 102 such as an STI (Shallow Trench Isolation) structure is first formed in a semiconductor substrate 101. Then, a recess 103 of a groove shape is formed in a predetermined region of the semiconductor substrate 101 as shown in FIG. 1B. A region where this recess 103 is formed represents a channel region of a transistor. Then, a gate insulating layer 104 is formed on a whole surface. Then, as shown in FIG. 1C, a gate polysilicon film 105 and a gate silicide film 106 are deposited on the gate insulating film 104 in this order. The gate silicide film 106 is exemplified by a tungsten silicide (WSi) film.
Next, as shown in FIG. 1D, a resist mask 107 for the gate electrode is formed on the gate silicide film 106. The resist mask 107 is formed on a channel region in which the recess 103 is formed. A displacement is present in position adjustment between the resist mask 107 and the channel region. As a result, as shown in FIG. 1E, the displacement exists between a position of a gate electrode 108 after an etching process and a position of the recess 103. Such a gate electrode 108 is used as a mask in an impurity ion implantation process to form diffusion layers (source/drain regions) 109 in the substrate 101. This will result in generation of an offset region 110 and a slit region 111 as shown in FIG. 1E. The offset region 110 is a region produced in the substrate 101 between the diffusion layer 109 and the recess 103, in which the impurity ions are not implanted. Meanwhile, the slit region 111 is a space produced in the recess 103 between the gate electrode 108 and the recess 103. FIG. 2 is a plan view showing a recess channel transistor formed as mentioned above. A cross section along A-A′ line in FIG. 2 is shown in FIG. 1E.
The offset region 110 and the slit region 111 degrade the transistor performance. Also, they cause a deviation in the threshold voltage Vt and a junction leakage current. Therefore, a technique is demanded which can prevent deterioration in characteristics of the recess channel transistor.